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| UP9503P 1 UP9503P-ds-f0000, june 2017 www.upi-semi.com 3/2/1+2/1/0-phase driver embedded pwm controller with smbus digital interface for amd svi2 gpu power ? ? ? ? ? amd svi2 gpu compliant ? ? ? ? ? rcot +tm control topology ? ? ? ? ? easy setting ? ? ? ? ? smooth mode transition ? ? ? ? ? fast transition response ? ? ? ? ? 2 integrated 12v mosfet drivers for vdd ? ? ? ? ? embedded bootstrap diode ? ? ? ? ? flexible operation phase configuration ? ? ? ? ? 3/2/1-phase pwm controller for vdd ? ? ? ? ? 2/1/0-phase pwm controller for vdda ? ? ? ? ? support operation phase disable function ? ? ? ? ? support 5+0 or 4+1 phase application ? ? ? ? ? smbus interface for performance and efficiency optimization ? ? ? ? ? dynamic programmable vr parameters ? ? ? ? ? programmable protection thresholds ? ? ? ? ? vr output reporting ? ? ? ? ? programmable loop gain ? ? ? ? ? programmable operation frequency ? ? ? ? ? inductor dcr current sensing for droop/ channel ocp/ total ocp ? ? ? ? ? differential current sense amplifier for current balance ? ? ? ? ? differential remote output voltage sense ? ? ? ? ? transient boost for fast transient response ? ? ? ? ? high accuracy dac ? ? ? ? ? ocp/uvp/ovp ? ? ? ? ? rohs compliant and halogen free general description features applications ? ? ? ? ? amd vga card gpu power supplies note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) p lating that are suitable for use in snpb or pb-free soldering processes. rebmunredr oe gakca pk ramer w gqp3059p ul 25-6x6nfqv ordering information the UP9503P is an amd svi2 compliant gpu voltage regulator controller that integrates a 3-phase pwm controller for vdd and a 2-phase controller for vdda. the vdd controller can be configured as 3/2/1-phase, and the vdda controller can be configured as 2/1/0-phase (0 denotes vdda controller is disabled) for platform power design flexibility. this part integrates 2 bootstrap diode embedded 12v mosfet drivers. for the typical 3+2-phase application, the 3-phase vdd controller has 2 embedded mosfet driver and 1 pwm output. the 2-phase vdda controller has 2 pwm outputs. the controller provides further flexible operating phase configurations to support 5+0 or 4+1 phase application (0 denotes vdda controller is disabled). the integrated smbus interface programmability makes this part with high performance and easy design. designer can define different power scenario for different current states to optimize the performance and efficiency. the UP9503P combines true differential output voltage sense, differential inductor dcr current sense, input voltage feed-forward sense and adaptive voltage positioning to provide accurately regulated power for gpu. it adopts upi proprietary rcot +tm (robust constant on-time) topology to have fast transient response and smooth mode transition. similar to digital based pwm controller, the loop gain is also programmable by smbus interface to achieve design flexibility. the UP9503P has built-in serial interface to communicate with amd svi2 compliant gpu. it supports mode transition function with various operating states. this part provides two different vid on-the-fly slew rates, which can be programmed by the smbus register. the UP9503P provides power good indicator and selectable vr parameters, such as smbus device address and vboot voltage. it also provides complete fault protection functions, including over voltage, under voltage, over current, over temperature and under voltage lockout. the UP9503P is available in vqfn6x6-52l package. pin configuration cspa csna 50 49 48 47 39 38 37 36 19 18 17 16 4 3 2 1 6 5 15 14 35 34 52 51 53 gnd 10 9 8 7 12 11 13 25 24 23 22 21 20 26 30 31 32 33 28 29 27 43 42 41 40 45 44 46 vcc12 ug1 b oot1 lg1 ph1 csn csp ug2 b oot2 lg2 ph2 tp eap dacfb vcc5 csp1 csn1 csp2 csp3 csn3 pwm1a csp1a csn1a p wrok csp2a csn2a pwm3 fbrtn en csn2 pok fba daca vinsen/tp a eapa fbrtna pwm2a imon comp tonse t imona vddio svt svd svc compa sclsda prog
UP9503P 2 UP9503P-ds-f0000, june 2017 www.upi-semi.com typical application circuit 3+2 phase application pwm3 boot2 boot1 12v vdd ug1 ph1 lg1 ug2 ph2 lg2 boot gnd pwm en vcc ph lg ug up1962 vdd_1 vdd_2 vdd_3 csp csn vdd_3 vdd_2 vdd_1 fb comp vdd_sense fbrtn vss_sense dac eap vcc5 csp1 csn1 ph1 vdd_1 csp2 csn2 ph2 vdd_2 csp3 csn3 ph3 vdd_3 svc svt svd svc svd svt imon imona cspa csna csp1a csn1a eapa daca compa fba vdda_sense vssa_sense pwm1a boot gnd pwm en vcc phlg ug up1962 vdda_1 pwm2a vdda_2 up1962 ph1a vdda_1 ph2a vdda_2 csp2a csn2a vdda_2 vdda_1 vdda tonset pok en pwrok vddio 12v 12v vcc12 prog tp vinsen/tpa boot gnd pwm en vcc phlg ug scl sda fbrtna gnd 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 1uf 12v_aux *note1 *note1: the 12v_aux is an auxiliary power for graphics cards. ph1a ph2a ph3 ph2 ph1 12v 12v 12v 52 5v 1 4847 50 49 46 45 75 43 2 31 6 5315 21 14 1918 17 9 8 10 12 13 36 51 16 11 25 24 23 22 20 44 43 42 41 40 39 38 37 26 30 29 28 27 32 33 34 35 UP9503P 3 UP9503P-ds-f0000, june 2017 www.upi-semi.com typical application circuit 4+1 phase application pwm3 boot2 boot1 v in vdd ug1 ph1 lg1 ug2 ph2 lg2 boot gnd pwm en vcc ph lg ug up1962 vdd_1 vdd_2 vdd_3 svc svt svd svc svd svt cspa csna eapa daca compa fba vdda_sense vssa_sense pwm1a boot gnd pwm en vcc phlg ug up1962 vdda_1 ph1a csp1a csn1a vdda pok en pwrok vddio v in csp csn vdd_3 vdd_2 vdd_1 ph1 vdd_1 ph2 vdd_2 ph3 ph4 vdd_3 vdd_4 sclsda pwm2a boot gnd pwm en vcc ph lg ug up1962 vdd_4 csp2a csn2a vdd_4 fb comp vdd_sens e fbrtn vss_sens e dac eap fbrtna csp1 csn1 csp2 csn2 csp3 csn3 vdda_1 vcc5 imon imona tonset 12v vcc12 prog tp gnd vinsen/tpa 5v 0.1uf 0.1uf 0.1uf 0.1uf 1uf 0.1uf 12v_aux *note1: the 12v_aux is an auxiliary power for graphics cards. *note 2: use 1kohm resistor to pull up csn1a to 5v. csp1a should be in normal connection. *note 2 *note 1 ph4 ph3 ph2 ph1 12v 12v 12v ph1a 5v 5248 47 4645 75 4 3 2 31 6 53 15 2114 19 18 17 9 8 1011 16 51 36 13 12 25 24 23 22 20 44 43 49 50 42 41 40 39 38 37 1 26 30 29 28 27 32 33 34 35 ph1a vdda_1 0.1uf UP9503P 4 UP9503P-ds-f0000, june 2017 www.upi-semi.com typical application circuit 5+0 phase application pwm3 boot2 boot1 v in vdd ug1 ph1 lg1 ug2 ph2 lg2 boot gnd pwmen vcc ph lg ug up1962 vdd_1 vdd_2 vdd_3 svc svt svd svc svd svt pok en pwrok vddio sclsda pwm1a boot gnd pwmen vcc ph lg ug up1962 vdd_4 fb comp vdd_sens e fbrtn vss_sens e dac eap vcc5 imon imona tonset 12v vcc12 prog tp gnd vinsen/tpa eapadaca compa fba left floating left floating fbrtna cspa csna 5v vdd_3 vdd_2 vdd_1 ph1 vdd_1 ph2 vdd_2 ph3 vdd_3 ph4 vdd_4 ph5 vdd_5 vdd_5 csp1 csn1 csp2 csn2 csp3 csn3 csp1a csn1a csp2a csn2a csp csn pwm2a boot gnd pwm en vcc ph lg ug up1962 vdd_5 0.1uf 0.1uf 0.1uf 0.1uf 1uf 12v_aux *note 2 *note 1 *note 2: use 1k ? resistor to pull up csna to 5v. connect cspa to ground. *note1: the 12v_aux is an auxiliary power for graphics cards. vdd_4 ph5 ph4 ph3 ph2 ph1 12v 12v 12v 5v 4546 75 4 3 2 31 6 53 15 2114 19 18 17 98 10 1116 51 36 13 12 37 38 39 40 41 42 48 4750 49 43 44 25 24 23 22 20 1 52 26 30 29 28 27 32 33 34 35 UP9503P 5 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 1a 2m w p .tuptuo m w p2esahpaddv .r evirdtefsomlanretxefotupnim w pehtotnipsihttcennoc .liaraddvrofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht 2a ntrbf .addvrofnruterkcabdeefegatlovtuptuo egatlovlaitnereffidehtottupnignitrevni .tnemerusaem egatlovtuptuoacadnitniopecnereferehtsiantrbf.reifil pmaesnes ,tniopesnesnruterkcabdeefegatlovtuptuorossecorpehto tyltceridnipsihttcennoc .esnes_assvyleman 3a cad .addvroftuptuo cad ehtrofegatlovecnereferehtsinipsihtfoegatlovtuptuoeh t morfroticapacatcennoc.antrbfottcepserhtiwderusaem siegatlovacad.liaraddv .antrbfotnipsiht 4a pae .addvrofreifilpmarorreehtfotupnignitrevni-non sihtneewtebrotsiseratcennoc .noitcnuf)enildaol(poordehttesotacaddnanip 5a bf .addvrofreifilpmarorreehtfotupnignitrevni 6a pt/nesniv .addvrofniptsetdnaesnesegatlovtupniegatsrewop lanoitcnuf-itlum asinipsiht gnitsetlanretniaddvrofosladna,esnesegatlovtupniegat srewoprofdesusiti.nip vtupniegatsrewopehtmorfredividegatlovrotsiseratcenn oc.esoprup ni .nipsihtot 7a pmoc addvrofreifilpmarorrepoollortnocfotuptuo ahtiwseiresnirotsiseratcennoc. .noitasnepmocpoollortnocegatlovrofdng otnipsihtmorfroticapac 8d vs .atad divlaires nevirdebnacdvs.rossecorpehtfotuptuoz-hgihhtiwllup-h supasidvs .esahptnemegdelwonkcaehtgnirudrvehtyb 9t vs .yrtemelet divlaires .rossecorpehtfotuptuollup-hsupasitvs 0 1c vs .kcolc divlaires .rossecorpehtfotuptuollup-hsupasicvs 1 1o iddv .ecafretniyromem ehtrofrossecorpehtrofecnerefereht roticapacatcennoc .sniptvs,dvs,cvsehtecnereferdnarewopotdng dnaoiddvneewteb 2 1a ds .tupniatadsubms .langisatadsublairesfotuptuorotupnisinipsiht 3 1l cs .tupnikcolcsubms tupnilangiskcolcsublairesseviecernipsiht . 4 1g orp nipgnittesnoitcnuf ehttesotdng ot5ccv morfredividegatlovrotsiseratcennoc. .sserddaecivedsubmsdnaaddvrof)toobv(egatlovputratsl aitini 5 15 ccv iucriclortnoccigolroftupniylppus naaivecruosegatlovv5aotnipsihttcennoc.t .tiucriclortnoccigolehtroftupniylppusehtsi5ccv.retl ifcr 6 1n e .tupnilortnocelbanepihc wolebnipsihtllup.pihcehtselbanev8.0evobanipsihtllup .pihcehtelbasidotv3.0 7 1a nomi addvrofgnisnesdnagnittesdlohserhtnoitcetorptnerrucr evo r otsiseratcennoc. r oticapacynatcennoctonod.dlohserhtnoitcetorptnerrucr evoehttesotdngotnipsihtmorf d aollatoteht.tnerrucdaollatotehtotlanoitroporpsinips ihtfotnerructuptuoeht.nipsihtot e htsekam dng otnipsihtmorfrotsiseradna,nipsihtfotuoswolfdnadesne ssitnerruc s deecxenipanominoegatlovehtnehw.tnerructuptuolatoteh totlanoitroporpegatlovanomi .rellortnocehtnwodtuhsotdeppirteblliwnoitcetorptner rucrevoeht,v65.2 8 1n omi ddvrofgnisnes dnagnittes dlohserhtnoitcetorptnerrucrevo r otsiseratcennoc. r oticapacynatcennoctonod.dlohserhtnoitcetorptnerrucr evoehttesotdngotnipsihtmorf d aollatoteht.tnerrucdaollatotehtotlanoitroporpsinips ihtfotnerructuptuoeht.nipsihtot nomiehtsekam dngotnipsihtmorfrotsiseradna,nipsihtfotuoswolfdnade snessitnerruc , v65.2sdeecxenipnominoegatlovehtnehw.tnerructuptuola totehtotlanoitroporpegatlov .rellortnocehtnwodtuhsotdeppirteblliwnoitcetorptner rucrevoeht UP9503P 6 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 9 1t esnot .gnittesemit-no m w p eht.emit-no m w pehttesotdngotnipsihtmorfrotsiseratcennoc .gnittesemit-no m w pemasehterahsrvaddvdnarv ddv 0 2p moc ddvrofreifilpmarorre poollortnocfotuptuo a htiwseiresnirotsiseratcennoc. .noitasnepmocpoollortnocegatlovrofdng otnipsihtmorfroticapac 1 2p t .ddvrofniptset .esoprupgnitsetlanretniddvrofdevreser 2 2b f .ddvrofreifilpmarorreehtfotupnignitrevni 3 2p ae ddvrofreifilpmarorreehtfotupnignitrevni-non dnanipsihtneewtebrotsiseratcennoc. noitcnuf)enildaol(poordehttesotcad . 4 2c ad .ddvroftuptuo cad .l iarddvehtrofegatlovecnereferehtsinipsihtfoegatlovtu ptuoeht . ntrbfotnipsihtmorfroticapacatcennoc.ntrbfottcepserh tiwderusaemsiegatlovcad 5 2n trbf .ddvrofnruter kcabdeefegatlovtuptuo e snesegatlovlaitnereffidehtottupnignitrevni n ipsihttcennoc.tnemerusaem egatlovtuptuocadnitniopecnereferehtsintrbf.reifilpm a .esnes_ssvyleman,tniopesnesnruterkcabdeefegatlovtup tuorossecorpehtotyltcerid 6 23 m w p .tuptuo m w p3esahp ddv .r evirdtefsomlanretxefotupnim w pehtotnipsihttcennoc .liarddvrofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht 7 22 toob .2esahp ddvrofrevirdetagreppurofylppuspartstoob r oftupniylppusehtsinipsiht croticapacpartstoobehttcennoc.revirdetagtefsomreppu eht toob n ip2toobneewteb e su.tefsomreppuehtnonrutotegrahcehtsedivorproticapac partstoobeht.nip2hpdna csacclm fu1.0tsaelta toob cerusekam dna, toob .rellortnocehtotesolcdecalpsi 8 22 gu .2esahp ddvroftuptuorevirdetagreppu reppufoetagehtotnipsihttcennoc otnehwenimretedotyrtiucricnoitcetorphguorht-toohseh tybderotinom sinipsiht.tefsom .tefsomreppuffo/nonrut 9 22 hp .2esahp ddvrofedon hctiws ,ecruostefsomreppufotniojehtotnipsihttcennoc tefsomreppurofdnuorgnruterehtsadesusinipsiht.niardt efsomrewoldnarotcudni otyrtiucricnoitcetorphguorht-toohsehtybderotinom sinipsihtnoegatlov.evirdgnitaolf .tefsomrewolehtnonrutotnehwenimreted 0 32 gl .2esahp ddvroftuptuorevirdetagrewol . tefsomrewolfoetagehtotnipsihttcennoc e htnonrutotnehwenimretedotyrtiucricnoitcetorphguorht -toohsehtybderotinom sinipsiht .tefsomreppu 1 32 1ccv .revirdtefsom deddebmeroftupniylppus dna,ecruosegatlovv21aotnipsihttcennoc 2 1ccv.nip21ccvehtotesolcyrevdecalpcclm fu0.1tsaeltahtiw dngotnipsihtssapyb etaglanretniroftnerrucseilppusnipsiht.srevirdtefsom deddebmeehtroftupniylppusehtsi .srevird 2 31 gl .1esahp ddvroftuptuorevirdetagrewol rewolfoetagehtotnipsihttcennoc otnehwenimretedotyrtiucricnoitcetorphguorht-toohseh tybderotinom sinipsiht.tefsom .tefsomreppuehtnonrut 3 31 hp .1esahpddvrofedonhctiws r otcudni,ecruostefsomreppufotniojehtotnipsihttcennoc g nitaolftefsomreppurofdnuorgnruterehtsadesusinipsiht .niardtefsomrewoldna e nimretedotyrtiucricnoitcetorphguorht-toohsehtybdero tinom sinipsihtnoegatlov.evird .tefsomrewolehtnonrutotnehw 4 31 gu .1esahp ddvroftuptuorevirdetagreppu . tefsomreppufoetagehtotnipsihttcennoc ff o/nonrutotnehwenimretedotyrtiucricnoitcetorphguorht -toohsehtybderotinom sinipsiht .tefsomreppu UP9503P 7 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 5 31 toob t.1esahp ddvrofrevirdetagreppurofylppuspartstoob t upniylppusehtsinipsih croticapacpartstoobehttcennoc.revirdetagtefsomreppu ehtrof toob 1 toobneewteb . tefsomreppuehtnonrutotegrahcehtsedivorproticapacpar tstoobeht.nip1hpdnanip csacclm fu1.0tsaeltaesu toob cerusekam dna, toob . rellortnocehtotesolcdecalpsi 6 3k op .noitacidnikorewop t ratsaddv/ddvehtsetacidnitahttuptuoniard-neponasinip siht .sneppahtluafondnatoobvegatlovtuptuootpu 7 31 psc .1esahp ddvroftupniesnestnerruclaitnereffidevitisop 8 31 nsc .1esahp ddvroftupniesnestnerruclaitnereffidevitagen 9 32 psc .2esahp ddvroftupniesnestnerruclaitnereffidevitisop t onsi2esahpddvnehw .noitarugifnocesahp-elgnisniderugifnocsirv ddvnehw dng otnipsihttrohs,desu 0 42 nsc .2esahp ddvroftupniesnestnerruclaitnereffid evitagen s i2esahp ddvnehw rv ddvtelot2m w pelbasidotrotsiser[k1ahguorht5ccvotnipsihthgihllup ,desuton .noitarugifnocesahp-elgnisnietarepo 1 43 psc .3esahp ddvroftupniesnestnerruclaitnereffidevitisop t onsi3esahpddvnehw .noitarugifnocesahp-2niderugifnocsirv ddvnehw dng otnipsihttrohs,desu 2 43 nsc .3esahp ddvroftupniesnestnerruclaitnereffidevitagen t onsi3esahpddvnehw k1ahguorht5ccvotnipsihthgihllup,desu ? rv ddvtelot3m w pelbasidotrotsiser .noitarugifnocesahp-2nietarepo 3 4p sc .ddvrofreifilpmaesnestnerruclatotfotupnignitrevni-n on 4 4n sc .ddvrofreifilpmaesnestnerruclatotfotupnignitrevni 5 4a nsc addvrofreifilpmaesnestnerruclatotfotupnignitrevni 6 4a psc addvrofreifilpmaesnestnerruclatotfotupnignitrevni-n on 7 4a 1nsc 1esahpaddvroftupniesnestnerruclaitnereffidevitagen s i1esahpaddvnehw. k1ahguorht5ccvotnipsihthgihllup,desuton ? addvtelota1m w pelbasidotrotsiser .noitarugifnocesahp-oreznietareporv 8 4a 1psc .1esahpaddvroftupniesnestnerruclaitnereffidevitisop s i1esahpaddvnehw .noitarugifnocesahp-orezniderugifnocsirvaddvnehw dng otnipsihttrohs,desuton 9 4a 2nsc .2esahpaddvroftupniesnestnerruclaitnereffidevitagen s i2esahpaddvnehw k1ahguorht5ccvotnipsihthgihllup,desuton ? addvtelota2m w pelbasidotrotsiser noitarugifnocesahp-elgnisnietareporv 0 5a 2psc .2esahpaddvroftupniesnestnerruclaitnereffidevitisop s i2esahpaddvnehw . noitarugifnocesahp-elgnisniderugifnocsirvaddvnehw dngotnipsihttrohs,desuton 1 5k or w p .noitacidnikorewop metsys r ewop metsysehtsetacidnitahthgihevitcaehtsinipsiht s kcolcgninnur-eerfdnasenalpegatlovllatahtsetacidniti ,detressasikor w pnehw.kosi noitacificepsnihtiwera 2 5a 1m w p .tuptuo m w p1esahp addv t efsomlanretxefotupnim w pehtotnipsihttcennoc addvrofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht.revird .liar dapdesopxe .dnuorg l ortnoccigoldnasrevirdtefsom deddebmefodnuorgehtsidapdesopxeeht .dng otdetcennocdnabcpegralaotderedlosebtsumtidna,stiucr ic UP9503P 8 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional block diagram pwrok por svi2/smbus/adc en on time generation and pwm control logic ramp generation tonset pwm3 fbrtn vddio prog svt scl sda csp1 csn1 dac vcc12 gnd fbrtna svd eap imon csn csp fb comp uvp ovp eap + 325mv svc eap - 325mv operation phase selection gm gm gm current balance gm per-phase ocp csp2 csn2 csp3 csn3 i csn i csn i csn daca i csna csp1a csn1a gm gm csp2a csn2a operation phase selection on time generation and pwm control logic current balance per-phase ocp eapa imona csna cspa fba compa uvp ovp eapa + 325mv eapa - 325mv gm i csna i csna tonset vcc12 d/a buf d/a buf ramp generation tonset gate control logic boot1 ug1 ph1 lg1 gate control logic boot2 ug2 ph2 lg2 pwm1 a pwm2 a tpa tpa tp vcc5 vinsen/tp a vinsen/tpa pok power ok UP9503P 9 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description power input and power on reset the UP9503P has two power inputs vcc5 and vcc12. vcc5 is the 5v supply input for control logic circuit of the controller. rc filter to vcc is required for locally bypassing this supply input. vcc12 is the supply power of two integrated 12v mosfet gate drivers. vcc5 and vcc12 have individual power on reset (por) function. the controller monitors the vcc12 voltage for pwm on-time calculation. en is the chip enable input pin. logic high to this pin enables the controller, and logic low to this pin disables the controller. the above four inputs (vcc5, vcc12, vinsen/tpa and en) are monitored to determine whether the controller is ready for operation. figure 1 shows the power ready detection circuit. the vcc5 voltage is monitored for power on reset with typically 4.3v threshold at its rising edge. the vcc12 voltage is monitored for power on reset with typically 10v threshold at its rising edge. the vinsen/tpa voltage is monitored for power on reset with typically 1v threshold at its rising edge. the vddio voltage is monitored for power on reset with typically 0.8v threshold at its rising edge. when vcc5, vcc12, vddio and vinsen/tpa are all ready, the controller waits for en to start up. when en pin is driven above 2v, the controller begins its start up sequence. when en pin is driven below 0.8v, the controller will be turned off, and it will clear all fault states to prepare to next start up once the controller is re-enabled. note that only vcc5 or en toggle will clear all fault state, vddio, vinsen/tpa or vcc12 toggle is not used for clearing fault state. anytime any one of the four inputs falls below their power on reset level will shutdown the controller. vcc5 vcc12 en vinsen/tpa 4.3v 10v 2v1v po r vddio 0.8v figure 1. circuit for power ready detection power-up sequence figure 2 shows a typical power-up sequence of UP9503P. when vcc5, vcc12, vddio and vinsen/tpa inputs are all ready, the controller waits for the en signal to initiate the power on sequence. after en goes high, the controller waits for a delay time t a (<1ms) then the output voltage starts to ramp up to vboot. the time interval t b is determined by the vid upward slew rate. the UP9503P asserts pok when vdd/vdda rails are in regulation of the voltage (vboot). v dd & vdda vcc5 vddio svc svd svt en pok pwrok boot-vid startup vid votf complete telemory telemory vcc12 t b t a figure 2. power up sequence timing initial start up voltage (vboot) and smbus device address (prog) refer to the table 1. the UP9503P determines the vboot voltage upon the svc and svd status during por. table 1. vboot voltage for both vdd and vdda cv sd v st oobv 00 v 1.1 01 v 0.1 10 v 9.0 11 v 8.0 the UP9503P features selectable initial start up voltage (vboot) and smbus device address for design flexibility. prog is a function setting pin, which is used to set the two essential parameters. refer to figure 3, connect a resistor voltage divider to the prog pin to set the initial start up voltage (vboot) for vdda and smbus device address. the vdda vboot can be set to 1.55v, 1.5v, 1.35v, and follow svi2 connections. the smbus device address can be set to 0x88h, or 0x8ah. table 2 shows the recommended resistance value for prog function setting. prog r 1 r 2 vcc5 figure 3 initial parameter setting UP9503P 10 UP9503P-ds-f0000, june 2017 www.upi-semi.com table 2. prog resistor setting addv )v(toobv subms sserdda k(eulavrotsiser2r/1r ? ) esahp2+ 3e sahp1+ 4e sahp0+5 1 r2 r1 r2 r1 r2 r 55. 18 82 9. 47 3. 31 6.4 24 8.6 1a na n 5. 18 87 2. 47 7. 33 3.1 23 8.8 1a na n 53. 18 86 7. 37 2. 42 8.8 14 3.1 2a na n 2ivs wollof snoitcennoc )1elbat( 8 87 3. 32 9. 44 8.6 12 6.4 21 3.0 31 3.44 55. 1a 85 0. 32 8. 54 2.5 11 .9 2a na n 5. 1a 88 7. 21 1. 71 9.3 16 5.5 3a na n 53. 1a 86 5. 24 1. 98 .2 12 7.5 4a na n 2ivs wollof snoitcennoc )1elbat( a 87 3. 28 .2 15 8.1 12 0.4 63 3.1 24 2.511 functional description operation phase disable function the UP9503P supports operation phase disable function to further increase the design flexibility. platform designer can choose to disable some phases to meet their design requirement. both vdd and vdda rail support operation phase disable function. the minimum operation phase number is 1+0-phase. in general, to disable a specific phase, pull up csnx to vcc5 through 1k ? resistor and tie cspx to ground for that phase. the controller detects all the csnx voltage at vcc5 power on reset to determine operation phase number. note that there is an exception for vdda rail phase disable function. to let vdda rail in zero-phase operation, pull up csna to vcc5 through 1k ? resistor and tied cspa to ground. table 4 shows the operation phase number setting. in addition, the operating phase number is governed by the svi2 command. the svi2 command and operating phase number are shown as table 3. table 3. svi2 command and vdd & vdda operating phase number l_0is pl _1is pr ebmunesahp ddvte sr ebmunesahpaddvtes 11 m ccesahpllu fm ccesahplluf 10 m ccesahpllu fm ccesahplluf 01 m ccesahp 1m ccesahp1 00 m spesahp 1m spesahp1 UP9503P 11 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description noitarugifnoc detroppus noitarepo esahp rebmun tegratotwolllup/hgihllup,noitcennocnip aps ca ns c3 ps c3 ns c2 ps c2 nsc a2ps ca 2ns ca 1ps ca 1nsc esahp-2+3 2+ 3- -- -- -- -- -- -- -- -- -- - 0+ 5d n g5 cc v- -- -- -- -- -- -- -- - 1+ 4- -- -- -- -- -- -- -- - )5eton( 5ccv 0+ 4d n g5 cc v- -- -- -- -- -- -d n g5 ccv 1+ 3- -- -- -- -- -- -d n g5 cc v- -- - 2+ 2- -- -d n g5 cc v- -- -- -- -- -- - 0+ 3d n g5 cc v- -- -- -- -d n g5 cc vd n g5 ccv 1+ 2- -- -d n g5 cc v- -- -d n g5 cc v- -- - 0+ 2d n g5 cc vd n g5 cc v- -- -d n g5 cc vd n g5 ccv 1+ 1- -- -d n g5 cc vd n g5 cc vd n g5 cc v- -- - 0+ 1d n g5 cc vd n g5 cc vd n g5 cc vd n g5 cc vd n g5 ccv .noitcennoclamronsetoned"--".1eton k1esu.2eton ? 5ccvotpu-llupnehwrotsiserpullup esahporezniliaraddvfonoitcnufelbasidesahpgnisunehwn oitcennocanscehtotnoitnettayap.3eton .noitarugifnoc noitcennocnwod/pullupniptcerrocnidnagnittesgorptcer rocni.elbasidesahprofelbatehtwollofyltcirts.4eton .pu-tratsgnirudtluafcihportsatacesuaclliw .noitcennoclamronniebdluohsa1psc,noitarepoesahp1+4r of.5eton table 4. operation phase number setting pwm on-time setting the pwm on-time is set by an external resistor r ton connected between tonset pin and gnd. the controller senses vcc12 voltage to obtain input voltage information for pwm on-time calculation. both the vdd rail and vdda rail share the same pwm on-time setting. the pwm on time can be calculated as below equation. 10 0 ? ? ? ? ? ? = ton in out on r v v t where t on is in ns, r ton is in k ? . table 5 lists the switching frequency and the recommended resistor r ton value (with condition: v in = 12v, v out = 1.2v). for example, given v in = 12v, v out = 1.2v, r ton = 49.9k ? , t on is about 500ns by above equation. the pwm frequency is about 200khz. note that the resistance value of r ton value must be greater than 10k ? to ensure the pwm on time calculation circuit in normal operation. table 5. switching frequency and resistor r ton ycneuqerfgnihctiws )zhk( rrotsiserdednem mocer not k( ? ) 00 29 .94 00 33 3 00 49 .42 00 50 2 00 66 1 rrotsiserfo muminim eht:eton not k01sieulav ? . UP9503P 12 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description dac reference voltage the UP9503P embeds separate precise bandgap reference voltage generation circuits for vdd and vdda controllers. figure 4 shows the reference voltage generation circuit. the output voltage of bandgap reference circuit is 1.55v with respect to fbrtn (fbrtna for vdda). the UP9503P utilizes plural resistors to generate precise reference voltages ranging from 6.25mv to 1.55v, with 6.25mv step. all the voltages connect to a multiplexer (mux). according to svi2 command, the mux outputs the selected vid (vdac) to the current limit buffer input. the dac voltage is generated as the reference voltage to the dac pin (daca pin for vdda). the dac voltage for vdda is generated by the same method except that it is referred to fbrtna pin. table 6 shows the vid voltage and the svi2 code. vbg fbrtn 1.55v fbrtn rn r2 r1 + - 1.55v 6.25mv mux 6.25mv~1.55v step=6.25mv vdac svi2 interface current limited buffer figure 4. reference voltage generation circuit dynamic vid change and slew rate the controller accepts setvid command via svi2 bus for output voltage change during normal operation. this allows the output voltage to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (vid otf). a vid otf event may occur under either light or heavy load condition. this voltage change direction can be upward or downward. the default value of vid upward slew rate is 12mv/us. the value of vid downward slew rate is 1/3 of vid upward slew rate. the upward slew rate of vdd and vdda can be separately further programmed by the controllers smbus register 0x26h. the upward slew rate can be set from 8mv/us to 22mv/us with a total of 7 steps and 2mv/lsb resolution. the default value of upward slew rate is 12mv/us. output voltage differential sense the UP9503P uses differential sense by a high-gain low offset error amplifier for output voltage differential sense as shown in figure 5. the gpu voltage is sensed by the fb and fbrtn pins (fba and fbrtna for vdda). fb pin is connected to the positive remote sense pin vdd_sense of the gpu via the resistor r fb . fbrtn pin is connected to the negative remote sense pin vss_sense of gpu directly. (vdda_sense and vssa_sense for vdda). the error amplifier compares the v fb with v eap (=v dac - i mon x r drp ) to regulate the output voltage. gm r comp_int comp fb r fb vdd_sense positive voltage remote sense pin of gpu csp csn eap dac r drp fbrtn c dac vss_sense negative voltage remote sense pin of gpu c comp r csn c csn reference voltage r comp i mon figure 5. output voltage differential sense total load current sense the UP9503P uses a low input offset current sense amplifier (csa) to sense the total load current flowing through inductors for droop function by csp and csn (cspa and csna for vdda) as shown in figure 6. r ph2 r ph3 1ohm ph1 ph2 ph3 1ohm 1ohm vdd_ 1 vdd_ 2 vdd_ 3 c csn r csn csp csn r ph1 i mon figure 6.total load current sense the voltage across c csn is proportional to the total load current, and the output current of csa (i mon ) is also proportional to the total load current of the voltage regulator. the sensed current i mon represents the total output current of the regulator, and it is directly used for droop function, total output over current protection, and output current reporting. i mon is calculated as follows. csn dc out mon r p r i i = in this inductor current sensing topology, r ph and c csn must be selected according to the equation below: p c r r l k csn ph dc = where r dc is the dcr of the output inductor l, p is the operation phase number. theoretically, k should be equal to 1 to sense the instantaneous total load current. but in real application, k is usually between 1.2 to 1.8 for better load transient response. note that the resistance value of r csn must be less than 2k ? to ensure the current sensing circuit in normal operation. UP9503P 13 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description table 6. vid table ]0:7[div s) v(egatlo v] 0:7[div s) v(egatlo v] 0:7[div s) v(egatlo v] 0:7[div s) v(egatlov 0000_000 00 0055. 10 000_010 00 0053. 10 000_001 00 0051. 10 000_011 00 0059.0 1000_000 05 7345. 11 000_010 05 7343. 11 000_001 05 7341. 11 000_011 05 7349.0 0100_000 00 5735. 10 100_010 00 5733. 10 100_001 00 5731. 10 100_011 00 5739.0 1100_000 05 2135. 11 100_010 05 2133. 11 100_001 05 2131. 11 100_011 05 2139.0 0010_000 00 0525. 10 010_010 00 0523. 10 010_001 00 0521. 10 010_011 00 0529.0 1010_000 05 7815. 11 010_010 05 7813. 11 010_001 05 7811. 11 010_011 05 7819.0 0110_000 00 5215. 10 110_010 00 5213. 10 110_001 00 5211. 10 110_011 00 5219.0 1110_000 05 2605. 11 110_010 05 2603. 11 110_001 05 2601. 11 110_011 05 2609.0 0001_000 00 0005. 10 001_010 00 0003. 10 001_001 00 0001. 10 001_011 00 0009.0 1001_000 05 7394. 11 001_010 05 7392. 11 001_001 05 7390. 11 001_011 05 7398.0 0101_000 00 5784. 10 101_010 00 5782. 10 101_001 00 5780. 10 101_011 00 5788.0 1101_000 05 2184. 11 101_010 05 2182. 11 101_001 05 2180. 11 101_011 05 2188.0 0011_000 00 0574. 10 011_010 00 0572. 10 011_001 00 0570. 10 011_011 00 0578.0 1011_000 05 7864. 11 011_010 05 7862. 11 011_001 05 7860. 11 011_011 05 7868.0 0111_000 00 5264. 10 111_010 00 5262. 10 111_001 00 5260. 10 111_011 00 5268.0 1111_000 05 2654. 11 111_010 05 2652. 11 111_001 05 2650. 11 111_011 05 2658.0 0000_100 00 0054. 10 000_110 00 0052. 10 000_101 00 0050. 10 000_111 00 0058.0 1000_100 05 7344. 11 000_110 05 7342. 11 000_101 05 7340. 11 000_111 05 7348.0 0100_100 00 5734. 10 100_110 00 5732. 10 100_101 00 5730. 10 100_111 00 5738.0 1100_100 05 2134. 11 100_110 05 2132. 11 100_101 05 2130. 11 100_111 05 2138.0 0010_100 00 0524. 10 010_110 00 0522. 10 010_101 00 0520. 10 010_111 00 0528.0 1010_100 05 7814. 11 010_110 05 7812. 11 010_101 05 7810. 11 010_111 05 7818.0 0110_100 00 5214. 10 110_110 00 5212. 10 110_101 00 5210. 10 110_111 00 5218.0 1110_100 05 2604. 11 110_110 05 2602. 11 110_101 05 2600. 11 110_111 05 2608.0 0001_100 00 0004. 10 001_110 00 0002. 10 001_101 00 0000. 10 001_111 00 0008.0 1001_100 05 7393. 11 001_110 05 7391. 11 001_101 05 7399. 01 001_111 05 7397.0 0101_100 00 5783. 10 101_110 00 5781. 10 101_101 00 5789. 00 101_111 00 5787.0 1101_100 05 2183. 11 101_110 05 2181. 11 101_101 05 2189. 01 101_111 05 2187.0 0011_100 00 0573. 10 011_110 00 0571. 10 011_101 00 0579. 00 011_111 00 0577.0 1011_100 05 7863. 11 011_110 05 7861. 11 011_101 05 7869. 01 011_111 05 7867.0 0111_100 00 5263. 10 111_110 00 5261. 10 111_101 00 5269. 00 111_111 00 5267.0 1111_100 05 2653. 11 111_110 05 2651. 11 111_101 05 2659. 01 111_111 05 2657.0 UP9503P 14 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description ]0:7[div s) v(egatlo v] 0:7[div s) v(egatlo v] 0:7[div s) v(egatlo v] 0:7[div s) v(egatlov 0000_000 10 0057. 00 000_010 10 0055. 00 000_001 10 0053. 00 000_011 10 0051.0 1000_000 15 7347. 01 000_010 15 7345. 01 000_001 15 7343. 01 000_011 15 7341.0 0100_000 10 5737. 00 100_010 10 5735. 00 100_001 10 5733. 00 100_011 10 5731.0 1100_000 15 2137. 01 100_010 15 2135. 01 100_001 15 2133. 01 100_011 15 2131.0 0010_000 10 0527. 00 010_010 10 0525. 00 010_001 10 0523. 00 010_011 10 0521.0 1010_000 15 7817. 01 010_010 15 7815. 01 010_001 15 7813. 01 010_011 15 7811.0 0110_000 10 5217. 00 110_010 10 5215. 00 110_001 10 5213. 00 110_011 10 5211.0 1110_000 15 2607. 01 110_010 15 2605. 01 110_001 15 2603. 01 110_011 15 2601.0 0001_000 10 0007. 00 001_010 10 0005. 00 001_001 10 0003. 00 001_011 10 0001.0 1001_000 15 7396. 01 001_010 15 7394. 01 001_001 15 7392. 01 001_011 15 7390.0 0101_000 10 5786. 00 101_010 10 5784. 00 101_001 10 5782. 00 101_011 10 5780.0 1101_000 15 2186. 01 101_010 15 2184. 01 101_001 15 2182. 01 101_011 15 2180.0 0011_000 10 0576. 00 011_010 10 0574. 00 011_001 10 0572. 00 011_011 10 0570.0 1011_000 15 7866. 01 011_010 15 7864. 01 011_001 15 7862. 01 011_011 15 7860.0 0111_000 10 5266. 00 111_010 10 5264. 00 111_001 10 5262. 00 111_011 10 5260.0 1111_000 15 2656. 01 111_010 15 2654. 01 111_001 15 2652. 01 111_011 15 2650.0 0000_100 10 0056. 00 000_110 10 0054. 00 000_101 10 0052. 00 000_111 10 0050.0 1000_100 15 7346. 01 000_110 15 7344. 01 000_101 15 7342. 01 000_111 15 7340.0 0100_100 10 5736. 00 100_110 10 5734. 00 100_101 10 5732. 00 100_111 10 5730.0 1100_100 15 2136. 01 100_110 15 2134. 01 100_101 15 2132. 01 100_111 15 2130.0 0010_100 10 0526. 00 010_110 10 0524. 00 010_101 10 0522. 00 010_111 10 0520.0 1010_100 15 7816. 01 010_110 15 7814. 01 010_101 15 7812. 01 010_111 15 7810.0 0110_100 10 5216. 00 110_110 10 5214. 00 110_101 10 5212. 00 110_111 10 5210.0 1110_100 15 2606. 01 110_110 15 2604. 01 110_101 15 2602. 01 110_111 15 2600.0 0001_100 10 0006. 00 001_110 10 0004. 00 001_101 10 0002. 00 001_1111 ffo 1001_100 15 7395. 01 001_110 15 7 393. 01 001_101 15 7391. 01 001_111 1f fo 0101_100 10 5785. 00 101_110 10 5783. 00 101_101 10 5781. 00 101_111 1f fo 1101_100 15 2185. 01 101_110 15 2183. 01 101_101 15 2181. 01 101_111 1f fo 0011_100 10 0575. 00 011_110 10 0573. 00 011_101 10 0571. 00 011_111 1f fo 1011_100 15 7865. 01 011_110 15 7863. 01 011_101 15 7861. 01 011_111 1f fo 0111_100 10 5265. 00 111_110 10 5263. 00 111_101 10 5261. 00 111_111 1f fo 1111_100 15 2655. 01 111_110 15 2653. 01 111_101 15 2651. 01 111_111 1f fo UP9503P 15 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description droop (load line) settingas shown in figure 5, the current i mon denotes the sensed total load current, which is mirrored to the eap pin. when load current increases, i mon also increases and creates a voltage drop across r drp , and makes v eap lower than the v dac as follows. dr p csn dc out dac drp mon dac eap r p r r i v r i v v ? ? ? ? ? ? = = where r dc is the dcr of output inductor, p is the operation phase number, and i out denotes the total load current. in steady state, the output voltage is regulated to v eap . as the total load current i out increases, i mon increases proportionally, making v eap decreases accordingly. this makes the output voltage also decreases linearly as the total output current increases, which is also known as active voltage positioning (avp). the slope of output voltage decrease to total load current increase is referred to as load line. the load line is defined as follows p r r r i v csn drp dc out out = ? ? = line l oad total output ocp and operating phase number as shown in figure 7, the sensed current i mon is mirrored internally and fed to imon pin (imona for vdda) for total output over current protection (ocp). a resistor r imon is connected from imon pin to gnd. this current flows through the resistor r imon , creating voltage drop across it. as the total load current increases, the voltage on imon pin (v imon ) increases proportionally. when the imon pin voltage further increases to greater than the ocp threshold (2.56v) for a specific delay time, the total output current protection will be triggered. pok will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the total output ocp is a latch-off type protection, and it can only be reset by vcc5 or en toggling. the total output ocp delay time can be further programmed by the smbus register. avoid adding capacitor to the imon pin. additional capacitance to this pin will affect the total output ocp. the default output current level of triggering total output ocp is calculated as follows. dc csn imon ocp out r r p r i = 56 .2 _ ocp i mon csp csn r csn c csn imon r imon 2.56v figure 7. total output ocp the total output ocp level is usually designed for the voltage regulator that is operated in full phase condition by hardware setting. the actual operating phase number is controlled by the svi2 command or the smbus auto phase setting. when the operating phase number is decreased, the total output ocp level is decreased as well. the total output ocp level is changed per actual operating phase number. table 7 shows the total output ocp ratio per actual operating phase number and the hardware configuration table 7. total output ocp and operating phase number oitar pcotuptuolatot noitidnocgnitarepo esahp- 5e sahp- 4e sahp- 3e sahp- 2e sahp-1 erawdrah noitarugifnoc esahp- 512 1/0 12 1/ 82 1/ 52 1/4 esahp- 4- -1 2 1/ 92 1/ 82 1/5 esahp- 3- -- -1 2 1/ 92 1/5 esahp- 2- -- -- -1 2 1/8 esahp- 1- -- -- - -- 1 UP9503P 16 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description per-phase over current protection in addition to the total output current ocp, the controller provides per-phase current ocp to protect the voltage regulator. the controller uses dcr current sensing technique to sense the inductor current in each phase for per-phase over current protection and current balance as shown in figure 8. in this inductor current sensing topology, the time constant can expressed as follows. cs x cspx dc c r r l k = where l is the output inductor, r dc is its parasitic resistance and k is a constant. theoretically, if k = 1, the sensed current signal i csnx can be expressed as follows. csnx dc lx csnx r r i i = v in lr dc vd d r cspx c csx r csnx cspx csnx i csnx i lx figure 8. phase current sense the sensed current i csnx represents the current in each phase, and it is compared to a current (default = 100ua, smbus programmable) for per-phase ocp. if the inductor current of any of the active operating phase exceeds the threshold for a specific delay time, the per-phase ocp is triggered. pok will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high- impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the per-phase ocp is a latch- off type protection, and it can only be reset by vcc5 or en toggling. the per-phase ocp threshold and its delay time can be further programmed by the smbus register. note that the resistance value of r csnx must be less than 2k ? to ensure the current sensing circuit in normal operation. the resistance of r csnx and the default per-phase ocp level can be obtained using equation as follows: ua r i r dc perphase ocp csnx 100 _ = over voltage protection (ovp) the controller monitors the voltage on fb pin (fba for vdda) for over voltage protection. after output voltage ramps up to vboot, the controller initiates ovp function. once v fb exceeds v eap + ovp threshold for a specific delay time, ovp is triggered. pok will be pulled low immediately, ugx will be held low, lgx will be held high, and pwm outputs will be low to let driver turns on low side mosfet and turns off high side mosfet to protect gpu. since the low side mosfet is turned on, the regulator output capacitor will be discharged and output voltage decreases as well. when fb pin voltage decreases to lower than typical 0.5v, lgx will be held low (pwm outputs turns to high impedance state) to turn off the low side mosfet to avoid negative output voltage. the other unaffected voltage regulator will also shut down. the ovp is a latch-off type protection, and it can only be reset by vcc5 or en toggling. the ovp detection circuit has a fixed delay time to prevent false trigger. the ovp threshold can be further programmed by the smbus register. under voltage protection (uvp) the controller monitors the voltage on fb pin (fba for vdda) for under voltage protection. after output voltage ramps up to vboot, the controller initiates uvp function. once v fb is lower than v eap - uvp threshold for a specific delay time, uvp is triggered. pok will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high-impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the uvp is a latch-off type protection, and it can only be reset by vcc5 or en toggling. the uvp detection circuit has a fixed delay time to prevent false trigger. the uvp threshold can be further programmed by the smbus register. power ok indication the UP9503P has a power ok indication pin for vdd/vdda controllers. the vdd/vdda controller monitors dac/daca voltage for power ok indication. when dac/daca voltage ramps to the target output voltage, the controller asserts pok. the pok is pulled low immediately if any of the faults (ocp, ovp and uvp) occurs. control loop the UP9503P adopts the upi proprietary rcot +tm control technology. the rcot uses the constant on-time modulator. the output voltage is sensed to compare with the internal high accurate reference voltage. the reference voltage is commanded by gpu through the svi2 interface or by system through smbus interface. the amplified error signal v comp is compared to the internal ramp to initiate a pwm on-time. the rcot +tm features easy design, fast transient response and is smooth mode transition and especially suitable for powering the microprocessor UP9503P 17 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description serial vid interface 2.0 (svi2) serial vid interface 2.0 (svi2) is a three wire (svc, svd and svt) serial synchronous interface defined by amd to transfer power management information between the gpu and the vr controller. the svi2 bus operates at a maximum frequency of 21mhz. gpu is always the master, and the vr controller is always the slave. svc, svd and svt pins are both in push-pull structure. svc is source synchronous clock signal from the gpu. only pwrok is asserted, svc and svd can be used to serially transmit data from the gpu to vr. smbus interface the UP9503P features an smbus interface and data registers to allow user to adjust various platform operating parameters for vdd and vdda. the supported operating parameters that can be adjusted through the smbus are summarized as table 8. the main function is to dynamically change the offset voltage, switching frequency, operating phase number, and load line according to the total load current. this function is referred to as auto phase, and it provides user the maximal flexibility in the platform design to maximize voltage regulators efficiency and the processor performance as well. for the 3-phase vdd regulator, there are three load current states (lcs) to set. the switching frequency, offset voltage, operating phase number and load line in each lcs can be programmed independently. for the 2-phase vdda regulator, there are two load current states (lcs) to set. the switching frequency, offset voltage and operating phase number in each lcs can also be programmed independently. vm0~ vm3 (avm0 for vdda): define the thresholds for six load current states (lcs0~lcs4) for vdd. the vdd controller converts imon pin voltage v imon to a digital content, which represents the total output current. the vmx setting is defined as the ratio of imon pin voltage to 2.56v (2.56v denotes when vdd output current reaches its summed total current). it takes 2.56v as the full scale, and 6-bits means that there are 64 steps for user to choose from. each load current state register has 6-bits to set the level of output current that the load current state is entered. the controller compares the vmx content and the i mon (refer to the section of total output over current protection ) to determine which load current state should be entered and executes the corresponding operating parameter settings (frequency, offset and operating phase number). lcs0: v imon > vm0, highest load current state lcs1: vm0 > v imon > vm1 lcs2: vm1 > v imon > vm2 lcs3: vm2 > v imon > vm3 lcs4: vm3 > v imon , lowest load current state. vm0_hys~ vm3_hys (avm0_hys for vdda) : define the hysteresis of vm0~vm3. the hysteresis is also defined as the ratio of imon pin voltage to 2.56v. vofs0~vofs4 (avofs0, avofs1 for vdda) : define the offset voltage in each load current state. 8-bits content setting with 6.25mv/step. iicf0~ iicf4 (aiicf0, aiicf1 for vdda) : define the switching frequency in each load current state. the switching frequency is defined as the ratio to current setting per r tonset and v in . the default is 1000 for 100%. 0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%; 0100 = 80%; 0101 = 85%; 0110 = 90%; 0111 = 95%; 1000 = 100%; 1001=125%; 1010 = 150%; 1011 = 175%; 1100 = 200%; 1101 = 225%; 1110 = 250%; 1111 = 275%. iicp0~iicp4 (aiicp0, aiicp1 for vdda) : define the operating phase number in each load current state. the operating phase number can be full-phase to single phase iicll0~ iicll4 (aiicll0, aiicll1 for vdda) : define the load line value in each load current state. the load line adjustment is defined as the ratio to current droop setting. the default is 0110 for 100%. 0000 = 0%; 0001 = 40%; 0010 = 60%;0011 = 70%; 0100 = 80%; 0101 = 90%; 0110 = 100%; 0111 =110%; 1000 = 120%;1001=130%; 1010 = 140%; 1011 = 150%; 1100 = 160%; 1101 =170%; 1110 = 180%; 1111 = 190%. rcomp1, rcomp2 (arcomp1, arcomp2 for vdda) : define the compensation resistor value. the compensation resistor value for the regulator operating in single-phase operation and multi-phase operation can be adjusted separately. gcomp (agcomp for vdda) : for ota transconductance setting for voltage control loop. it is defined as the ratio to the default value of 2020 ua/v. oc/uv/ov: oc/uv/ov is used for the threshold adjustment of per-phase ocp, uvp and ovp, respectively. ocp delay : for total ocp threshold and per-phase ocp delay time setting. lchvid (alchvid for vdda) : this register stores the 8-bits vid code. when latch vidfunction is enabled, controller will ignore the setvid command from gpu and move output voltage to the targeted value. imon (imona for vdda) : the register reports real imon value (ffh when v imon = 2.56v). vfb (vfba for vdda) : this register reports the output voltage that is converted by the internal adc with 6.25mv/lsb. UP9503P 18 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description table 8. smbus configuration register .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 10x 0d dv ]2:7[0mv w/ rh 00 0levelegatlovnomilanretnites )etatstnerructsehgih(0scl>=0level>nomiv eract'nod:]0:1[tib 65.2x)46/]2:7[tib(=0mv v65.2otegatlovnomiotoitarehtsadenifedsignittes0mv 20x 0d dv ]2:7[1mv w/ rh 00 1levelegatlovnomilanretnites 1scl>=1level>nomiv 2scl>=1level UP9503P 20 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed f0x 0d dv ]0:7[3sfov w/ rh 00 )pets/vm52.6(.3sclddvfotesffoegatlov tesffoevitagen="1";tesffoevitisop="0",tibngissi7tib vm057-/+=stimilrewoldnareppu vm0+=00000000 vm52.6+=10000000 vm573+=00111100 vm057+=00011110 vm057+=11111110 vm0-=00000001 vm52.6-=10000001 vm573-=00111101 vm057-=00011111 vm057-=11111111 01x 0d dv ]0:7[4sfov w/ rh 00 )pets/vm52.6(.4sclddvfotesffoegatlov tesffoevitagen="1";tesffoevitisop="0",tibngissi7tib vm057-/+=stimilrewoldnareppu vm0+=00000000 vm52.6+=10000000 vm573+=00111100 vm057+=00011110 vm057+=11111110 vm0-=00000001 vm52.6-=10000001 vm573-=00111101 vm057-=00011111 vm057-=11111111 21x 0d dv ]4:7[0fcii ]0:3[1fcii w/ rh 88 gnittesycneuqerfnoitarepo ddv %001=tluafed,0sclddvforebmunesahp:]4:7[tib %001=tluafed,1sclddvforebmunesahp:]0:3[tib ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%571=110;%051=0101;%521=1001;)tluafed(%001=0001 %572=1111;%052=0111;%522=1011;%002=0011 31x 0d dv ]4:7[2fcii ]0:3[3fcii w/ rh 88 gnittesycneuqerfnoitarepo ddv %001=tluafed,2sclddvforebmunesahp:]4:7[tib %001=tluafed,3sclddvforebmunesahp:]0:3[tib ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%571=110;%051=0101;%521=1001;)tluafed(%001=0001 %572=1111;%052=0111;%522=1011;%002=0011 41x 0d dv ]4:7[4fcii w/ rh 88 gnittesycneuqerfnoitarepo ddv %001=tluafed,4sclddvforebmunesahp:]4:7[tib ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%571=110;%051=0101;%521=1001;)tluafed(%001=0001 %572=1111;%052=0111;%522=1011;%002=0011 UP9503P 21 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 51x 0d dv ]4:7[0llcii ]0:3[1llcii w/ rh 66 gnittesenildaolddv %001=tluafed,0sclddvfognittesenildaol:]4:7[tib %001=tluafed,1sclddvfognittesenildaol:]0:3[tib ;%08=0010;%07=1100;%06=0100;%04=1000;%0=0000 ;%021=0001;%011=1110;)tluafed(%001=0110;%09=1010 ;%061=0011;%051=1101;%041=0101;%031=1001 %091=1111;%081=0111;%071=1011 61x 0d dv ]4:7[2llcii ]0:3[3llcii w/ rh 66 gnittesenildaolddv %001=tluafed,2sclddvfognittesenildaol:]4:7[tib %001=tluafed,3sclddvfognittesenildaol:]0:3[tib ;%08=0010;%07=1100;%06=0100;%04=1000;%0=0000 ;%021=0001;%011=1110;)tluafed(%001=0110;%09=1010 ;%061=0011;%051=1101;%041=0101;%031=1001 %091=1111;%081=0111;%071=1011 71x 0d dv ]4:7[4llcii w/ rh 66 gnittesenildaolddv %001=tluafed,4sclddvfognittesenildaol:]4:7[tib ;%08=0010;%07=1100;%06=0100;%04=1000;%0=0000 ;%021=0001;%011=1110;)tluafed(%001=0110;%09=1010 ;%061=0011;%051=1101;%041=0101;%031=1001 %091=1111;%081=0111;%071=1011 81x 0d dv ]7[ne_bc ]4:6[niagi_1hp ]0:2[niagi_2hp w/ rh 44 ,noitcnufecnalabtnerrucddvfolortnocffo/no:]7[tib ffo="1",no="0",no=tluafed %001=tluafed,tsujdaniagecnalabtnerruc1esahpddv:]4:6 [tib %001=001;%5.78=110;%57=010;%5.26=100;%05=000 %5.731=111;%521=011;%5.211=101;)tluafed( eract'nod:]3[tib %001=tluafed,tsujdaniagecnalabtnerruc2esahpddv:]0:2 [tib %001=001;%5.78=110;%57=010;%5.26=100;%05=000 %5.731=111;%521=011;%5.211=101;)tluafed( 91x 0d dv ]4:6[niagi_3hp w/ rh 44 eract'nod:]7[tib %001=tluafed,tsujdaniagecnalabtnerruc3esahpddv:]4:6 [tib %001=001;%5.78=110;%57=010;%5.26=100;%05=000 %5.731=111;%521=011;%5.211=101;)tluafed( eract'nod:]3[tib b1x0 ddv ]4:6[soi_1hp ]0:2[soi_2hp w/ rh 00 eract'nod:]7[tib au0=tluafed,tesffoecnalabtnerruc1esahpddv:]4:6[tib ;au8=001;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101 eract'nod:]3[tib au0=tluafed,tesffoecnalabtnerruc2esahpddv:]0:2[tib ;au8=001;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101 c1x 0d dv ]4:6[soi_3hp w/ rh 00 eract'nod:]7[tib au0=tluafed,tesffoecnalabtnerruc3esahpddv:]4:6[tib ;au8=001;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101 eract'nod:]3[tib UP9503P 22 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed e1x 0d dv ]4:7[1pmocr ]0:3[2pmocr w/ rh 37 gnittesrotsiserpmocr pmocrnoitarepoesahp-elgnis:]4:7[tib k02=tluafed,)]4:7[+1(xk5.2=pmocr pmocrnoitarepoesahp-itlum:]0:3[tib k01=tluafed,)]0:3[+1(xk5.2=pmocr f1x 0d dv ]0:3[pmocg w/ rh 08 noitceleseulavmgato ddv noitceleseulavmgato ddv:]3[pmocg lliwgnittes]0:2[pmocg,)v/au0202(eulavtluafedesuotec rof=0 ;)tluafed(derongieb ]0:2[pmocgniteseulavehtesu=1 llaotdeilppa,gnittesmgecnatcudnocsnartddv:]0:2[pmoc g ) v/au0202=(tluafedotoitarehtsadenifed,rebmunesahpgni tarepo ;x54.1=110;x13.1=010;x71.1=100;)tluafed(x1=000 x33.0=111;x6.0=011;x18.0=101;x96.1=001 02x 0d dv ]0:7[divhcl w/ rh 84 v1.1=h84=tluafed.retsigerdivhctalddv 12x 0d dv ]0:7[nomi o r- - gnitropernomiddv 22x 0d dv ]0:7[bfv o r- - gnidaeregatlovddv t uptuolautcafotluserd/amorfsi]0:7[bfvniseulavgnidaer egatlov .tluafedybegatlov 32x 0d dv ]0:6[dni_tcetorp o rh 00 dereggirtsinoitcetorphcihwgnitacidni,rotacidninoitc etorpddv eract'nod:]7[tib rotacidnipvo:]6[tib evitca="1",evitcaton="0" rotacidnipvu:]5[tib evitca="1",evitcaton="0" rotacidnipco:]4[tib evitca="1",evitcaton="0" rotacidnipcoesahprep:]3[tib evitca="1",evitcaton="0" 1=]3[tibfirotacidnipcoesahprep:]0:2[tib 3hp=110;2hp=010;1hp=100 5hp=101;4hp=001 1=]3[tibnehwylnodilavsi]0:2[tibfoeulavtroper 42x 0d erahs yaledpco ]0:6[ w/ rh 23 gnittesemasehterahsaddvdnaddvhtob eract'nod:]7[tib emityaledpcolatot:]4:6[tib ;)tluafed(su02=110;su51=010;su01=100;su5=000 su04=111;su53=011;su03=101;su52=001 eract'nod:]3[tib emityaledpcoesahprep:]0:2[tib ;su01=001;su8=110;)tluafed(su6=010;su4=100;su2=000 su61=111;su41=011;su21=101 52x 0d erahs vo/vu/co ]0:5[ w/ rh 00 gnittesemasehterahsaddvdnaddvhtob eract'nod:]7[tib tnerrucpcoesahprep:]4:5[tib au061=11;au041=01;au021=10;)tluafed(au001=00 dlohserhtpvu:]2:3[tib vm075=11;vm584=01;vm504=10;)tluafed(vm523=00 dlohserhtpvo:]0:1[tib vm075=11;vm584=01;vm504=10;)tluafed(vm523=00 UP9503P 23 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 62x 0d erahs ]4:6[rs_rva ]0:2[rs_rv w/ rh 22 eract'nod:]7[tib noitcelesetarwelsdrawpudiv-dddv:]4:6[tib noitcelesetarwelsdrawpudiv-daddv:]0:2[tib . su/vm22ot8morfegnargnittes.noitcelesetarwelsdrawpud ivd .su/vm21sitluafed.bsl-repsu/vm2dnaspets7latot ;)tluafed(su/vm21=010;su/vm01=100;su/vm8=000 ;su/vm02=011;su/vm81=101;su/vm61=001;su/vm41=110 ;su/vm22=111 72x 0d dv ]0:7[1csim w/ rh f0 2lortnocsfo:]7[tib 1=]4[tibnehwylnodilavsi]7[tibfoeulavtroper subms+2ivs="1",submsylno="0" lortnoccadv:]6[tib 2ivserongi="1",2ivswollof="0" lortnocetatsrwp:]5[tib 2ivserongi="1",2ivswollof="0" 1lortnocsfo:]4[tib ]7[tibwollof="1",2ivswollof="0" lortnocpcolatot:]3[tib )tluafed(elbane="1",elbasid="0" lortnocpcoesahp-rep:]2[tib )tluafed(elbane="1",elbasid="0" lortnocpvo:]1[tib )tluafed(elbane="1",elbasid="0" lortnocpvu:]0[tib )tluafed(elbane="1",elbasid="0" 82x 0d dv ]0:7[2csim w/ rh 40 lortnocenildaol:]7[tib 2ivswollof="0" 2ivserongi="1" ycneuqerfgnihctiwsrofmurtcepsdaerps:]6[tib )tluafed(murtcepsdaerpselbasid="0" murtcepsdaerpselbane="1" .gersubmsfoecruosatadehtfonoitceles:]5[tib )]0:7[bfv(gnidaeregatlovtuptuoddvh22x0 )tluafed(d/amorf="0" 2ivsmorf="1" lortnocelbaneesahpotua:]4[tib )tluafed(esahpotuaelbasid="0" esahpotuaelbane="1" lortnocelbaneenildaol:]3[tib )tluafed(enildaolelbane="0" )0=ll(enildaolelbasid="1" lortnocelbanemsp:]2[tib mspelbasid="0" )tluafed(mspelbane="1" lortnocelbanemsu:]:1[tib )tluafed(msuelbasid="0" msuelbane="1" UP9503P 24 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 92x0 ,ddv derahs ]6[2nepto w/ rh 54 )nwodtuhslamrehtrellortnoc(lortnocelbane)lanretni(p to:]6[tib ,)tluafed(elbane="1",elbasid="0" eract'nod:]5[tib a2x 0d erahs ]5:7[dw tuoemit_cvs ]0:2[ w/ rh 50 remitgodhctaw )tluafed(elbasid="0";elbane="1":]7[tib sutatsgodhctaw:]6[tib doirepgodhctawnihtiwderruccosnoitcasnartsubms="0" doirepgodhctawsdeecxenoitcasnartsubmsneewtebemit="1 " snoitcasnartsubmsonfi,delbanesinoitcnufgodhctawehtn ehw retsigerlla,)sm0021rosm006(doirepdetcelesanihtiwruc co submsybderaelcsitibsiht.eulavtluafedottesereblliwst netnoc .retsigersihtmorfdaer doirepgodhctaw:]5[tib )tluafed(sm006="0" sm0021="1" ;...;su2=010;su1=100;su5.0=000:]0:2[tib:tuoemit_cvs su46=111;su23=011 e2x 0d dv pmoc_pmar ]0:7[ w/ rh 88 %001=tluafed,noitarepoesahp-itlumrofsi]4:7[pmoc_pma r ;%08=0010;%57=1100;%07=0100;%56=1000;%06=0000 ;)tluafed(%001=0001;%59=1110;%09=0110;%58=1010 ;%521=1011;%021=0011;%511=1101;%011=0101;%501=1001 %531=1111;%031=0111 %001=tluafed,noitarepoesahp-elgnisrofsi]0:3[pmoc_pm ar ;%08=0010;%57=1100;%07=0100;%56=1000;%06=0000 ;)tluafed(%001=0001;%59=1110;%09=0110;%58=1010 ;%521=1011;%021=0011;%511=1101;%011=0101;%501=1001 %531=1111;%031=0111 f2x 0d dv ]0:7[mt w/ r- - .gnidaereulavrotinomlamrehtsubmsddv nipnestrofnoisrevnocd/afoeulavehtserotsretsigersiht 03x 0a ddv ]2:3[0pciia ]0:1[1pciia w/ rh 50 gnittesrebmunesahpnoitarepoaddv 0scladdvforebmunesahp:]2:3[tib 1scladdvforebmunesahp:]0:1[tib esahp1:00;esahp2:10 UP9503P 25 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 13x 0a ddv ]0:7[0sfova w/ rh 00 )pets/vm52.6(.0scladdvfotesffoegatlov .tesffoevitagen="1";tesffoevitisop="0",tibngissi7ti b vm057-/+=stimilrewoldnareppu vm0+=00000000 vm52.6+=10000000 vm573+=00111100 vm057+=00011110 vm057+=11111110 vm0-=00000001 vm52.6-=10000001 vm573-=00111101 vm057-=00011111 vm057-=11111111 23x 0a ddv ]0:7[1sfova w/ rh 00 )pets/vm52.6(.1scladdvfotesffoegatlov .tesffoevitagen="1";tesffoevitisop="0",tibngissi7ti b vm057-/+=stimilrewoldnareppu vm0+=00000000 vm52.6+=10000000 vm573+=00111100 vm057+=00011110 vm057+=11111110 vm0-=00000001 vm52.6-=10000001 vm573-=00111101 vm057-=00011111 vm057-=11111111 33x 0a ddv ]2:3[0fciia ]0:1[1fciia w/ rh 88 gnittesycneuqerfnoitarepoaddv %001=tluafed,0scladdvforebmunesahp:]4:7[tib %001=tluafed,1scladdvforebmunesahp:]0:3[tib ;%08=0010;%57=1100;%07=0100;%56=1000;%06=0000 ;)tluafed(%001=0001;%59=1110;%09=0110;%58=1010 ;%002=0011;%571=1101;%051=0101;%521=1001 %572=1111;%052=0111;%522=1011 43x 0a ddv ]2:3[0llciia ]0:1[1llciia w/ rh 66 gnittesenildaoladdv %001=tluafed,0scladdvfognittesenildaol:]4:7[tib %001=tluafed,1scladdvfognittesenildaol:]0:3[tib ;%08=0010;%07=1100;%06=0100;%04=1000;%0=0000 ;%021=0001;%011=1110;)tluafed(%001=0110;%09=1010 ;%061=0011;%051=1101;%041=0101;%031=1001 %091=1111;%081=0111;%071=1011 53x 0a ddv ]7[ne_bca niagi_1hpa ]4:6[ niagi_2hpa ]0:2[ w/ rh 44 , no=tluafed,noitcnufecnalabtnerrucaddvfolortnocffo/n o:]7[tib ffo="1",no="0" %001=tluafed,tsujdaniagecnalabtnerruc1esahpaddv:]4: 6[tib %001=001;%5.78=110;%57=010;%5.26=100;%05=000 %5.731=111;%521=011;%5.211=101;)tluafed( eract'nod:]3[tib %001=tluafed,tsujdaniagecnalabtnerruc2esahpaddv:]0: 2[tib %001=001;%5.78=110;%57=010;%5.26=100;%05=000 %5.731=111;%521=011;%5.211=101;)tluafed( UP9503P 26 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed 63x 0a ddv ]4:6[soi_1hpa ]0:2[soi_2hpa w/ rh 00 eract'nod:]7[tib au0=tluafed,tesffoecnalabtnerruc1esahpaddv:]4:6[tib ;au8=001;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101 eract'nod:]3[tib au0=tluafed,tesffoecnalabtnerruc2esahpaddv:]0:2[tib ;au8=001;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101 73x 0a ddv ]4:7[1pmocra ]0:3[2pmocra w/ rh 37 gnittesrotsiserpmocra pmocranoitarepoesahp-elgnis:]4:7[tib k02=tluafed,)]4:7[+1(xk5.2=pmocra pmocranoitarepoesahp-itlum:]0:3[tib k01=tluafed,)]0:3[+1(xk5.2=pmocra 83x 0a ddv ]0:3[pmocga w/ rh 00 noitceleseulavmgatoaddv noitceleseulavmgatoaddv:]3[pmocga lliwgnittes]0:2[pmocga,)v/au0202(eulavtluafedesuote crof=0 ;)tluafed(derongieb ]0:2[pmocganiteseulavehtesu=1 llaotdeilppa,gnittesmgecnatcudnocsnartaddv:]0:2[pmo cga ) v/au0202=(tluafedotoitarehtsadenifed,rebmunesahpgni tarepo ;x54.1=110;x13.1=010;x71.1=100;)tluafed(x1=000 x33.0=111;x6.0=011;x18.0=101;x96.1=001 93x 0a ddv pmoc_pmara ]0:7[ w/ rh 88 %001=tluafed,noitarepoesahp-itlumrofsi]4:7[pmoc_pma ra ;%08=0010;%57=1100;%07=0100;%56=1000;%06=0000 ;)tluafed(%001=0001;%59=1110;%09=0110;%58=1010 ;%521=1011;%021=0011;%511=1101;%011=0101;%501=1001 %531=1111;%031=0111 %001=tluafed,noitarepoesahp-elgnisrofsi]0:3[pmoc_pm ara ;%08=0010;%57=1100;%07=0100;%56=1000;%06=0000 ;)tluafed(%001=0001;%59=1110;%09=0110;%58=1010 ;%521=1011;%021=0011;%511=1101;%011=0101;%501=1001 %531=1111;%031=0111 a3x 0a ddv ]0:7[anomi o r- - gnitroperanomiaddv b3x 0a ddv ]0:7[abfv o r- - gnidaeregatlovaddv lautcafotluserd/amorfsi]0:7[abfvniseulavgnidaeregat lov .tluafedybegatlovtuptuo c3x 0a ddv ]0:7[1csima w/ rh f0 2lortnocsfo:]7[tib 1=]4[tibnehwylnodilavsi]7[tibfoeulavtroper subms+2ivs="1",submsylno="0" lortnoccadv:]6[tib 2ivserongi="1",2ivswollof="0" lortnocetatsrwp:]5[tib 2ivserongi="1",2ivswollof="0" 1lortnocsfo:]4[tib ]7[tibwollof="1",2ivswollof="0" lortnocpcolatot:]3[tib )tluafed(elbane="1",elbasid="0" lortnocpcoesahp-rep:]2[tib )tluafed(elbane="1",elbasid="0" lortnocpvo:]1[tib )tluafed(elbane="1",elbasid="0" lortnocpvu:]0[tib )tluafed(elbane="1",elbasid="0" UP9503P 27 UP9503P-ds-f0000, june 2017 www.upi-semi.com functional description .ger .rdda sucof liar eman.ge rs secc at luafe dn oitpircsed d3x 0a ddv ]0:7[2csima w/ rh 40 lortnocenildaol:]7[tib 2ivserongi="1",2ivswollof="0" ycneuqerfgnihctiwsrofmurtcepsdaerps:]6[tib )tluafed(murtcepsdaerpselbasid="0" murtcepsdaerpselbane="1" .gersubmsfoecruosatadehtfonoitceles:]5[tib )]0:7[abfv(gnidaeregatlovtuptuoaddvhb3x0 )tluafed(damorf="0" 2ivsmorf="1" lortnocelbaneesahpotua:]4[tib )tluafed(esahpotuaelbasid="0" esahpotuaelbane="1" lortnocelbaneenildaol:]3[tib )tluafed(enildaolelbane="0" )0=ll(enildaolelbasid="1" lortnocelbanemsp:]2[tib mspelbasid="0" )tluafed(mspelbane="1" lortnocelbanemsu:]:1[tib )tluafed(msuelbasid="0" msuelbane="1" e3x 0a ddv tohrv_pmeta ]0:4[ w/ rh 50 eract'nod:]7[tib eract'nod:]6[tib eract'nod:]5[tib lortnocelbane#tohrv:]4[tib elbasid="1",)tluafed(elbane="0 19morfegnarpmet,bslybtfeltfihs:]0:3[tib o 121otc o c 601=tluafed o 3,c o bsl/c ;bsl2tfihs=0100;bsl1tfihs=1000;tfihson=0000 )tluafed(bsl5tfihs=1010;bsl4tfihs=0010;bsl3tfihs=11 00 ;bsl8tfihs=0001;bsl7tfihs=1110;bsl6tfihs=0110 bsl01tfihs=0101;bsl9tfihs=1001 f3x 0a ddv ]0:7[divhcla w/ rh 84 v1.1=h84=tluafed,retsigerdivhctaladdv 44x 0a ddv ]0:7[0mva w/ rh 00 0scl>=0level>anomiv esahp-2rof()etatstnerructsewol(1scl>=0level UP9503P 29 UP9503P-ds-f0000, june 2017 www.upi-semi.com (note 1) supply input voltage vcc12 to gnd ------------------------------------------------------------------------------------------- -- -0.3v to +15v supply input voltage vcc5 to gnd -------------------------------------------------------------------------------------------- ---- -0.3v to +6v vinsen/tpa ------------------------------------------------------------------------------------------------------------------- --------------- -0.3v to +6v bootx to phx ----------------------------------------------------------------------------------------------------------------------- -0.3v to +15v phx to gnd dc ------------------------------------------------------------------------------------------------------------------------------------ -0.7v to +15v < 200ns ------------------------------------------------------------------------------------------------------------------------------- -8v to +30v bootx to gnd dc ------------------------------------------------------------------------------------------------------------------------ -0.3v to +(vcc12+15v) < 200ns ---------------------------------------------------------------------------------------------------------------------- ------- -0.3v to +42v ugx to phx dc --------------------------------------------------------------------------------------------------------------- -0.3v to +(bootx-phx+0.3v) < 200ns ----------------------------------------------------------------------------------------------------------- -5v to +( bootx-phx+0.3v) lgx to gnd dc ------------------------------------------------------------------------------------------------------------------------ -0.3v to +(vcc12+15v) < 200ns -------------------------------------------------------------------------------------------------------------------- -5v to +(vcc12+0.3v) other pins to gnd ------------------------------------------------------------------------------------------------------------- ------------- -0.3v to +6v storage temperature ra nge ----------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------- --------------------------- 150 o c lead temperature (soldering, 10 sec) ----------------------------------------------------------------------------------------- ------------------- 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- ------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 200v package thermal resistance (note 3) vqfn6x6 - 52l ja ---------------------------------------------------------------------------------------------------------------------- 35 o c/w vqfn6x6 - 52l jc ----------------------------------------------------------------------------------------------------------------------- 3 o c/w power dissipation, p d @ t a = 25 o c vqfn6x6 - 52l ---------------------------------------------------------------------------------------------------------------------------------- 2.86w (note 4) operating junction temperature range ------------------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature range ------------------------------------------------------------------------------------------- -40 o c to +85 o c supply input v oltage vcc12 ---------------------------------------------------------------------------------------------------- ------- 10.8v to 13.2v supply input v oltage vcc5 ---------------------------------------------------------------------------------------------------- --------- 4.5v to 5.5v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. UP9503P 30 UP9503P-ds-f0000, june 2017 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus dlohserhtrop5cc vr op 5ccv gnisir5cc v1 . 43 . 45 . 4v siseretsyh rop5cc vs yh rop5ccv - -3 . 0- -v tnerrucylppu si 5ccv ,v0= divaddvdnaddv,v5=ne gnihctiwson m w p - -0 1- -a m tnerrucnwodtuh si ndhs_5ccv v0=n e- -0 6- -a u tupniylppus21ccv dlohserhtrop21cc vr op 21ccv gnisir21cc v- -0 1- -v siseretsyh rop21cc vs yh rop21ccv - -2- -v tnerrucylppu si 21ccv ,v0= divaddvdnaddv,v5=ne gnihctiwson m w p - -0 5 2- -a u tnerrucnwodtuh si ndhs_21ccv v0=n e- -- -0 6a u tupniapt/nesniv dlohserhtropapt/nesni vr op r_nesniv gnisirapt/nesni v- -1- -v dlohserhtropapt/nesni vr op f_nesniv gnillafapt/nesni v- -5 . 0- -v tupnine woltupn iv li - -- -8 . 0v hgihtupn iv hi 2- -- -v tnerruc wol-llu pi lp_ne 12 3 a u )ngisedybdeetnaraug(sretemarapgnimitsub2ivs doirep cv st doirep 6.7 4- -- -s n ycneuqerf cv sf cvs 1. 0- -1 2z hm emithgih cv st hgih 0 2- -- -s n emitwolcv st wol 0 3- -- -s n cvsotemitputestvs,dvs egdegnisir t putes 5- -- -s n cvs morfemitdlohtvs,dvs egdegnillaf t dloh 5- -- -s n cvsotemittratstvs,dvs egdegnillaf t trats 5 1- -- -s n cvs morfemitpotstvs,dvs egdegnisir t pots 5- -- -s n emitllaf,tvs,dvs,cv st llaf v cd_ho vot cd_lo - -- -1s n emitesir,tvs,dvs,cv st esir v cd_lo vot cd_ho - -- -1s n (vcc5 = 5v, vcc12 = 12v, t a = 25 o c, unless otherwise specified) UP9503P 31 UP9503P-ds-f0000, june 2017 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu 2ivs tupnikorwpdnatvs,dvs,cvs egatlovwol v cd_li 0- - *53.0 oiddv v tupnikorwpdnatvs,dvs,cvs egatlovhgih v cd_hi *7.0 oiddv -- oiddv v korwpdnatvs,dvs,cvs egatlovsiseretsyh v tsyh *1.0 oiddv - -- - v tuptuolevelwoltvs,dvs,cvs egatlov v lo 0- -2 .0 v tuptuolevelhgihtvs,dvs,cvs egatlov v ho oiddv 2.0- -- oiddv v tnerructuptuotvs,dvs,cv si ho vgnivirdnehw ho 4- -- - am tupnikorwp,tvs,dvs,cvs tnerrucegakael i l 001- -- 001 au egakaeltuptuozhgih dvs tnerruc i zo 001 -- -0 01 au secnaticapactupnitvs,dvs,cv sc ni ngisedybdeetnaraug - -- -5 fp cdadnayrtemelet ycarucca cda v2.1otv8. 01 -- - 1 bsl v8.0 UP9503P 34 UP9503P-ds-f0000, june 2017 www.upi-semi.com en (5v/div) vdd (500mv/div) pok (5v/div) vdda (500mv/div) en (5v/div) vdd (500mv/div) pok (5v/div) vdda (500mv/div) svc (2v/div) vdd (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdd (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdd (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdd (500mv/div) svt (2v/div) svd (2v/div) typical operation characteristics vdd vr dynamic vid up time : 10us/div vid = 1v to 1.2v, i load = 45a power on from en time : 100us/div v in = 12v, no load power off from en time : 1ms/div v in = 12v, i out = 1a vdd vr dynamic vid up time : 10us/div vid = 0.4v to 1v, i load = 9a vdd vr dynamic vid up time : 10us/div vid = 1v to 1.06875v, i load = 45a vdd vr dynamic vid up time : 10us/div vid = 1v to 1.1v, i load = 45a UP9503P 35 UP9503P-ds-f0000, june 2017 www.upi-semi.com ugate1 (20v/div) vdd (1v/div) pok (5v/div) i out (50a/div) ugate1 (20v/div) v fb (1v/div) pok (5v/div) lgate1 (10v/div) vdd (100mv/div) svc (2v/div) vdd (500mv/div) svt (2v/div) svd (2v/div) vdd vr dynamic vid up time : 10us/div vid = 1v to 1.4v, i load = 45a typical operation characteristics vdd vr load transient time : 10us/div f load = 10khz, vdd = 1v, i load = 35a ~ 120a vdd vr ovp time : 4us/div vdd vr ocp time : 200us/div UP9503P 36 UP9503P-ds-f0000, june 2017 www.upi-semi.com vdda (100mv/div) svc (2v/div) vdda (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdda (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdda (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdda (500mv/div) svt (2v/div) svd (2v/div) svc (2v/div) vdda (500mv/div) svt (2v/div) svd (2v/div) vdda vr dynamic vid up time : 10us/div vid = 1v to 1.4v, i load = 20.5a vdda vr load transient time : 10us/div f load = 10khz, vdda = 1v, i load = 20a ~ 60a typical operation characteristics vdda vr dynamic vid up time : 10us/div vid = 1v to 1.2v, i load = 20.5a vdda vr dynamic vid up time : 10us/div vid = 0.4v to 1v, i load = 4.1a vdda vr dynamic vid up time : 10us/div vid = 1v to 1.06875v, i load = 20.5a vdda vr dynamic vid up time : 10us/div vid = 1v to 1.1v, i load = 20.5a UP9503P 37 UP9503P-ds-f0000, june 2017 www.upi-semi.com ugate1a (20v/div) vdda (1v/div) pok (5v/div) i out (50a/div) ugate1a (20v/div) v fba (1v/div) pok (5v/div) lgate1a (10v/div) typical operation characteristics vdda vr ovp time : 4us/div vdda vr ocp time : 200us/div UP9503P 38 UP9503P-ds-f0000, june 2017 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. vqfn6x6 - 52l package 5.90 - 6.10 pin 1 mark bottom view - exposed pad 0.15 - 0.25 4.40 - 4.60 0.35 - 0.45 5.90 - 6.10 0.00 - 0.05 0.20 ref 0.80 -1.00 0.31 - 0.41 0.13 - 0.23 UP9503P 39 UP9503P-ds-f0000, june 2017 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2016, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064 |
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